1. Field of the Invention
The present invention relates to the field of semiconductor processing, and more particularly to a method of forming a semiconductor pattern capable of reducing micro-loading effects.
2. Description of the Prior Art
Dynamic random access memory (DRAM) is a kind of volatile memory, which is constituted by a plurality of memory cells. Each memory cell is mainly constituted by one transistor and one capacitor controlled by a transistor, and each memory cell are electrically connected by the word line (WL) and bit line (BL).
In order to improve the operation speed of the dynamic random access memory, and to meet consumer demand for miniaturization of electronic devices, the channel length of the transistor of the dynamic random access memory needs to be shorten. However, others issues may be happened, such as short channel effects, the on current loss and other problems.
Accordingly, in order to overcome the above problems, in recent years, the vertical transistor structure replaces the horizontal transistor structure, for example, the vertical transistor structure is formed in a deep trench in the substrate. In this way, the operating speed and the volume can be improved, and the short channel effect and other issues can also be prevented. However, the general vertical transistor used in structural design still needs to be improved, it is one of the goals researched in this field.